A Hall-effect device, or Hall device in short, also known as a Hall element or Hall sensor, is a device that converts the component to be measured of a magnetic field vector into a voltage. Hall devices are currently the most used magnetic sensors. They are commercially available both as discrete devices and integrated circuits incorporating a combination of a Hall device, current source, amplifier, and other signal conditioning electronic circuits. The principle of operation and basic technology of Hall devices are described in the book by R. S. Popovic, entitled “HALL EFFECT DEVICES”, Institute of Physics Publishing, Bristol and Philadelphia 2004.
Briefly, there are two classes of Hall devices, which are known as horizontal Hall devices and vertical Hall devices. A horizontal Hall device has the form of a plate, which is usually disposed in parallel with the active chip surface, and is sensitive to a magnetic field running perpendicular to the active chip surface. A vertical Hall device usually does not have a plate-like geometry, but it behaves like a plate disposed vertically with respect to the active chip surface, and it is sensitive to a magnetic field running parallel to the active chip surface.
FIG. 1 shows a cross-section and FIG. 2 shows a plan view of a vertical Hall device 1 of the prior art. In order to avoid confusion, the following convention is used. In all figures showing a plan view of the vertical Hall device, axes x and y oriented orthogonally to each other are used to indicate the direction in which a “length” or a “width” is measured. Any distance along the x-axis, such as L in FIG. 2, will be called a length; and any distance along the y-axis, such as W in FIG. 2, will be called a width. This convention will be applied independently of the ratio of the length and the width of the structure under consideration.
The vertical Hall device 1 is fabricated with an IC (integrated circuit) technology: It has an N-type region 2 which is implanted into a P-type region 3 which may be a P-type substrate. Four heavily doped N+ regions arranged along a straight line 8 are disposed at the surface of the N-well NW and form electrical contacts 4 to 7. The N-well NW has a depth dNW, the N+ contacts have a depth d+. The vertical Hall device 1 has a length L and a width W. Two non-neighboring contacts of the vertical Hall device 1 are used as input terminals and the other two non-neighboring contacts are used as output terminals. For example, the contacts 4 and 6 can be used as the input terminals and the contacts 5 and 7 as the output terminals, or vice versa. The electrical resistances R1, R2, R3 and R4 between the contacts 4 to 7 of the Hall device 1 can be represented by a Wheatstone bridge as shown in FIG. 3. As a part of the invention, the resistance R2 is considered to be composed of two resistances R2′ and R2″ with R2=R2′ ∥R2″.
The Hall device 1 is supplied with a constant current Iin, or with a constant voltage Vin via the input terminals. If the Hall device 1 is exposed to a magnetic field having a component perpendicular to the effective device plane, then the electromotive force of the Hall effect acts between the output terminals. The voltage Vout, which appears between the output terminals, is called the output voltage of the Hall device 1. The output voltage of a Hall device is given by the following expressions:Vout=Voff+SI×Iin ×B, or Vout=Voff +SV×Vin×B  (1)where Voff denotes an offset voltage, SI denotes the current-related sensitivity, B denotes the component of a magnetic field perpendicular to the effective device plane, and SV denotes the voltage-related sensitivity.
In order to be suitable for a practical application as a magnetic field sensor, a Hall device should have the following main characteristics:    a) Low offset: For example, in a silicon integrated Hall device, the offset voltage Voff should be Voff<0.01×Vin.    b) Convenient common output voltage level: The voltages Vout,1 and Vout,2 of the output terminals should be at about the middle of the input voltage Vin: Vout,1≈½Vin and Vout,2≈½Vin.    c) Exchangeability of the input and output terminals: The Hall device characteristics, including the absolute value of the offset voltage, the common level of the output voltage, the input and output resistances, and the magnetic sensitivity should stay nearly equal when the contacts 4 and 6 are used as input terminals and the contacts 5 and 7 as output terminals and when the contacts 5 and 7 are used as input terminals and the contacts 4 and 6 as output terminals. The exchangeability of the input and output terminals of a Hall device is the prerequisite for the application of a technique for the reduction of the offset voltage of the Hall device known as the spinning-current technique.    d) High magnetic sensitivity: Trends go to operate modern sensor systems at a low supply voltage; therefore, the most relevant sensitivity figure of merit of a Hall device is usually SV, not SI. For example, for a silicon integrated Hall device, the voltage-related magnetic sensitivity SV should be SV>0.03V/VT (volt per volt and tesla).    e) Low flicker noise (also known as 1/f noise): For example, at a Hall device supply voltage Vin of Vin=1V, the corner frequency fc of the flicker noise (where the 1/f part of the noise spectral density equals the thermal noise) should be fc<10 kHz.
The requirements a) through c) will be met if the four resistances R1, R2, R3, R4 are all approximately equal. The voltage-related magnetic sensitivity (requirement d) is a complex function of the characteristics of the material used for the Hall device and of its geometry. But roughly speaking, the requirement d) is easier to meet if the resistances R1, R2, R3, R4 have equal values and are “short”. Here “short” means that the length of a resistor is not greater than the square root of its cross-sectional area. The flicker noise (requirement e) depends much on the quality of the material used for the Hall device, and on the quality and protection of its surface.
Theoretically, any two-dimensional (planar) horizontal Hall device can be transformed by a mathematical technique known as conformal mapping into a vertical Hall device. But the calculated dimensions of the contacts are nearly impossible to meet in reality.
Therefore, when designing an integrated vertical Hall device, it is a serious challenge to meet simultaneously all the requirements a) to e). In all known designs of the four-contact vertical Hall device, the resistance between the two outer contacts 4 and 7 is much larger than the resistance between the two inner contacts 5 and 6, i.e. R4>>R2, as can be recognized from FIG. 1. This inequality produces an offset voltage as large as half of the input voltage. The big difference between the resistances R2 and R4 is due to various limitations of the actual CMOS technologies, the main two limitations being the following:    (i) A small depth dNW of the N-well NW with respect to the length L of the vertical Hall device 1 (usually dNW/L<<1). It can be shown by conformal mapping that the nominal size of the inner contacts 5 and 6 would be very small and below the limits of actual CMOS technologies.    (ii) A substantial depth d+ of the N+ contact regions compared to the small distance 12 between the inner contacts 5 and 6. A consequence of this fact is that the resistance R2 consists of a parallel connection of two resistances: R2′, which represents the resistance for a current flowing between the side-walls of the two N+ regions of the inner contacts 5 and 6 very near and parallel to the device surface; and a resistance R2″, which represents the resistance for a current flowing between the two inner contacts 5 and 6 at a “normal” depth below the device surface. The resistance R2 of the parallel connected resistances R2′ and R2″ is smaller than that of the “normal” R2″, which makes the problem of the inequality of R2 and R4 still worse.
Similar problems exist also in a five-contact vertical Hall device implemented in a CMOS technology.